快速中值滤波算法研究及其FPGA硬件实现

Research of Fast Median Filtering Algorithm and Hardware Implementation Based on FPGA

针对图像噪声大和对比度差特点,提出了一种水下图像快速中值滤波算法及FPGA硬件实现。通过分析中值滤波算法,以3×3窗口为数学模型,以CycloneⅢ EP3C40F324I7为核心处理芯片,用VHDL语言实现模型中所需要的模块,实现了快速中值滤波算法对图像的处理。通过硬件实验结果对比,系统达到了抑制噪声保持原图像的目的。该设计在水下图像处理中具有一定的工程参考及应用价值。

For noise and contrast poor characteristics,a underwater image research of fast median filtering algorithm and hardware implementation was proposed based on FPGA.Through analysis median filter algorithm,the mathematical model of 3×3 template as an example,and CycloneⅢEP3C40F324I7 as the core processing chip.The design of every needed models using VHDL realized the image processing as fast median filtering algorithm.Through the hardware experimental results show that the purposed system reduces the noise and maintains the original image.The design has a certain reference and application value.