一种基于FPGA的RS解码方法的实现

Design of RS Decoding Technology Based on FPGA

RS码作为一种具有很强纠错能力的BCH码,同时它更是一类最强大并被广泛使用的前向纠错码。针对常用RS解码实现出现的延时及资源占用较大的问题,本设计采用改进的能够有效避免除法回路的BM算法实现RS解码中的关键方程求解,在研究改进BM算法基础上,增加不大的资源占用的同时,有效提高其处理速度。

As a BCH code with the very error-correcting ability,RS code is also one of the most powerful and widely used forward error-correcting code. In order to solve the problem of delay and resource occupancy in common RS decoding, this design adopts the improved BM algorithm which can effectively avoid the divide circuit to solve the key equation solving in RS decoding. On the basis of improving the BM algorithm,while increasing the resources occupying, effectively improving its processing speed.