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基于NSGA-Ⅱ算法的IP核测试优化研究

Optimization of IP cores test based on NSGA-Ⅱ algorithm
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摘要 IP核集成化的SoC测试,测试时间与测试功耗是两个相互影响的因素。多目标进化算法能够处理相互制约的多目标优化问题。在无约束条件下,对IP核的测试时间与测试功耗建立联合优化模型,并采用多目标进化算法中的改进型非劣分类遗传算法(Non-dominated Sorting Genetic Algorithm Ⅱ,NSGA-Ⅱ)对模型进行求解。通过应用ITC'02标准电路中的h953做应用验证,结果表明该方法能够给出模型的均衡解,证明了模型的实用性和有效性。 In the test of SoC integrated IP cores, test time and test power were in the restrict condition to each other. The multi-objective evolutionary algorithm can achieve the simultaneous optimization. The paper constructed the combined optimization model for IP cores~ test time and test power under no constraining, applied NSGA-II to deal with the combined optimization model, and adopted ITC'02 Benchmark circuit h953 to verify the algorithm. The results show that the NSGA-II algorithm can generate balance solutions, and the test model is practical and effective.
作者 黄俊
出处 《电子设计工程》 2017年第17期58-61,共4页 Electronic Design Engineering
关键词 NSGA—II算法 IP核 测试时间 测试功耗 NSGA-II IP cores test time test power
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