基于码流的软件控制FPGA故障注入系统

A Software Controlled FPGA Fault Injection System Based on Bitstream

基于静态随机存储器的现场可编程逻辑门阵列应用于航天电子系统时,易受到单粒子翻转效应的影响,存储数据会发生损坏。为评估器件和电路在单粒子翻转效应下的可靠性,提出一种基于TCL脚本控制的故障注入系统,可在配置码流层面模拟单粒子翻转效应。介绍了该故障注入系统的实现机制和控制算法,并将该软件控制方法与传统硬件控制方法进行对比分析。设计了一种关键位故障模型,从设计网表中提取关键位的位置信息,缩小了故障注入的码流范围。在Virtex-5开发板XUPV5-LX110T上的故障注入实验表明,该故障注入系统能有效模拟单粒子翻转效应,与传统随机位故障注入相比,关键位故障注入的故障率提高了近5倍。

SRAM-based field programmable gate arrays（ FPGA） are susceptible to single event upset（ SEU） when they are used in aerospace electronic systems,and as a result,the stored data is always corrupted. In order to evaluate the reliability of FPGA device and circuit under the SEU,a fault injection system based on TCL script was proposed to simulate the behavior of SEU upon the configuration bitstream. The implementation mechanism and control algorithm of the proposed fault injection system were introduced,and the software controlled method was compared with the traditional hardware controlled method. In addition,an essential-bit fault model was proposed to extract the position information of essential bits from the design netlist,which had reduced the bitstream range of fault injection. Experiment on Virtex-5 development board XUPV5-LX110 T showed that the software controlled fault injection system could simulate the SEU effectively,and the failure rate of essential bit fault injection was improved by nearly 5 times compared with that of the traditional random bit fault injection system.