一种结合高精度TDC的快速全数字锁相环

A Fast All Digital Phase-locked Loop with High Precision TDC

针对传统全数字锁相环锁相周期长、时间数字转换电路量化误差较大等问题,提出了一种在高分辨率时间数字转换器的基础上能够快速锁相的全数字锁相环.本设计提出的相调模块将量化的相位差还原成时间序列,并在状态机的控制下加入到重构信号中,从而能够在检测到相位差之后的最多两个输入参考时钟周期内使相位一次性对齐,锁相时间控制在0.72μs之内;设计的上升沿检测电路能够在重构与参考信号同频时,准确地检测两者上升沿是否同时到来并给出相应的使能信号,从而在锁相时关闭时间数字转换电路,大大降低了电路的功耗;优化了多时钟多相位的时间数字转换器粗量化的计算方法,提高了粗量化速度,增大了计数器位宽,扩大了测量范围,并且量化误差控制在0.25ns之内.最后完成了整体设计的RTL级建模及仿真,结果证明,该全数字锁相环具有锁相速度快、量化精度高、稳定性好、功耗低、输出频率便于调整等特点.

As the traditional all digital phase-locked loop has the shortcomings such as a long period of lock phase and a large quantization error of TDC, this paper proposes a fast digital phase-locked loop based on high resolution TDC. The new design characterizes that the phase adjustment circuit makes the quantized phase difference restore to time series, which can comprehensively consider the reconstruction signal under the control of the state machine.In this case, the phase can be aligned for the maximum of two reference clock periods, and the phase lock time is controlled within 0.72 μs when the phase difference is detected.Meanwhile, when the reconstructed signal and the reference one are at the same frequency, the ris- ing edge detection circuit can accurately detect whether the rising edges of signals are arriving simultane- ously or not, and can generate the suitable enable signal to turn off the TDC circuit reducing the power con- sumption. Moreover, the design optimizes the coarse quantization method of TDC with multi-clocks and multi-phase and increases the measuring range.Additionally, the quantization error is controlled within 0.25 ns.Finally, the whole design is modeled in the RTL level and simulated,which shows that the new all digital phase-locked loop has the high speed of locking phase, high precision, high stability, low power consump- tion,and convenience to adjust the output frequency.