摘要
为了改进传统的基于ROM查找表法的DDS结构,在得到相同性能的模拟信号输出的同时节省硬件资源,提出采用CORDIC算法改进传统的DDS结构。首先详述DDS原理与传统ROM结构的优缺点,设计了一种基于CORDIC算法的多级流水线结构的DDS。然后运用verilog语言编写RTL级代码,在Modelsim下仿真完成后,在Xilinx公司的开发板ML605上进行综合验证,将输出的数字信号通过AD9739实现模拟输出,并通过频谱仪和示波器观察其输出性能。结果表明,使用CORDIC算法改进后的DDS运算速度更快,同时节省了大量FPGA硬件资源。
To improve the traditional DDS structure based on the ROM lookup table method and save the hardware resources while simulating the output of the same performance, CORDIC algorithm is proposed. Firstly, the DDS principle and the advantages and disadvantages of traditional ROM structure are described in detail, and based on CORDIC algorithm, DDS in multi-stage pipeline structure is designed. Then RTL code is written in verilog language. After simulation in Modelsim, synthesized verification is done on Xilinx development board ML605, and the simulating output is acquired via the output digital signal, passing through AD9739. And the output performance is observed by spectrum analyzer and oscilloscope. The experimental results indicate that the CORDIC algorithm could improve the speed of DDS operation and save a lot of FPGA hardware resources.
出处
《通信技术》
2017年第8期1642-1646,共5页
Communications Technology