基于40nm超大规模SoC芯片存储器测试电路设计与实现

MBIST Design for the 40nm SoC Chip

针对超大规模SoC(System on Chip)芯片中存储器的测试需求,首先分析存储器测试中存在的主要问题,包括新故障模型和新算法的需求、对电路性能的影响、以及测试成本的增加等。针对上述问题,存储器测试电路设计中,综合考虑PPA(Power Performance Area)等多个设计因素优化测试电路,包括BIST(Build-in-Self Test)电路布局、数量、时序、存储器布图规划等。最后在一款40 nm量产SoC芯片上,应用Mentor Graphics公司LV(Logic Vision)流程实现了测试电路设计,实验结果证明本方案的可行性和有效性。

The MBIST technology is common used for the memory test of SoC （ System on Chip） chip. But some problems are found about the technique when the chip semiconductor manufacturing process is to 40 nm, such as the fault model and the testing algorithm need to be renew for the new fault occurred in the manufacturing process. For these problems, a new MBIST design based on Mentor Graphics Corporation LV （Logic Vision）processis proposed. The PPA（ Power Performance Area）factors have been considered to get an optimized MBIST circuit in the design. This design circuit has been used in a 40 nm SoC chipand declared its feasibility.