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基于单稳态结构的时钟丢失检测电路设计

Design of the Missing Clock Detector Circuit Based on the Monostable Structure
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摘要 单片机可以看成是在时钟驱动下的时序逻辑电路,单片机工作过程中,所有的工作都是在时钟信号控制下进行的。针对MCU的硬件监控技术及复位系统,依据单稳态结构特性,设计一款时钟丢失检测电路。该电路采用电流源取代电阻的方式,实现单稳态电路的阻容结构。电路上电使能后,监测时钟上升沿,通过时钟上升沿的触发,使电路保持单稳态工作状态。采用0.25μm CMOS工艺进行仿真,仿真结果显示,如果时钟保持在高电平或低电平的时间大于258.4μs时,单稳态电路将超时,并产生一个复位信号。此电路结构简单,便于集成在MCU复位系统,可对系统时钟进行丢失监测。 Single-chip microcontroller may be regarded as the sequential logic circuit driven by clock, in which all the work was conducted under the clock signal control.According to the hardware monitoring technology of MCU and reset system, a missing clock detector circuit based on the structural char- acteristics of monostable is designed,which uses the current source to replace the resistance, and realizes the resistance-capacitance structure of the monostable circuit. After the circuit being powered on, clock rising edge is monitored, which maintains a monostable working state by triggering the clock rising edge. Using the 0.25μm CMOS technology to the simulation, the simulation results show that if the time of the clock holding in high level or low level is greater than 258.4μs, the monostable circuit will time out, and generate a reset singal. The circuit structure is simple, which is easy to integrate in the MCU reset system and can monitor the system missing clock.
作者 李月香
出处 《微处理机》 2017年第4期20-22,共3页 Microprocessors
关键词 时钟丢失 单稳态 触发器 单片机 复位系统 时钟监测 Missing Clock Monostable Tigger Microcontroller Reset system Clock monitoring
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  • 1姚茂群,沈继忠,朱志刚.单稳态触发器的结构及其开关级设计原理[J].电路与系统学报,2005,10(6):84-87. 被引量:6
  • 2刘晓阳.单稳态触发器及其工程应用[J].济南职业学院学报,2006(1):41-42. 被引量:3
  • 3Rabaey J M.数字集成电路设计透视[M].北京:清华大学出版社,1999.672-684.
  • 4艾伦P E 霍尔伯格D R.CMOS模拟电路设计[M].北京:科学出版社,1995..
  • 5Fairchild products. NE555 Datasheet[K]. 2002.
  • 6Jan M. Rabaey, Anantha Chandrakasan,Borivoje Nikolic;Digitial Integrated Circuit[M].北京:电子工业出版社:155-158.
  • 7Abou-Seido, A.I.'Nowak, B. Chu C. Fitted Elmore Delay:a Simple and Accurate Interconnect Delay Model[C]//IEEE International Conference on 16-18 Sept. 2002:422-427.
  • 8Sapatnekar S S. RC Interconnect Optimization under the Elmore Delay Model [J]. Design Automation, 1994. 31st Conference on 6-10 June 1994: 387-391.
  • 9Yamakoshi K. Ino M. Generalised Elmore Delay Expression for Distributed RC Tree Networks[J]. Electronics Letters, 1 April 1993,29(7) : 617-618.
  • 10徐丽燕,毕净,沈继忠.双边沿单稳态触发器的设计[J].浙江大学学报(理学版),2003,30(6):646-650. 被引量:5

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