65 nm CMOS工艺时钟发生器的设计与实现

Design and Implementation of a 65 nm CMOS Clock Generator

设计了一款应用于高速片上系统(System-on-Chip,SoC)领域的时钟发生器电路.基于Delta-sigma调制技术实现了小数分频,同时引入了加抖技术(Dither)以及模数转换器(Digital to Analog Converter,DAC)补偿技术,从而大幅度地抑制了Delta-sigma调制引起的量化噪声.基于65nm CMOS工艺完成了电路设计,仿真结果表明,当输出频率为典型应用的1.2GHz时,该电路周期抖动(period jitter)的均方根值(rms)约为0.656ps,功耗仅为约3.824mW.

Abstract： This paper introduces a clock generator intended for the use in a high-speed SoC design. Fractional division achieved through the employment of Delta-sigma modulation. Significantly suppression of quantization error, which is caused by the Delta-sigma modulation, obtained through the use of dithering and DAC compensation technology. Circuit design implemented based on a 65 nm CMOS process and the simulation result shows that the period jitter （rms） and the total power are 0. 656 ps and 3. 824 roW, respectively, when the output frequency is 1.2 GHz of a typical application.