一种基于分段电容的低功耗SARADC设计

A Low Power SAR ADC Design Based on Segmented Capacitor

针对当前物联网技术对功耗的严格要求,设计了一种基于分段电容的低功耗SAR ADC电路.电路通过使用分离电容阵列来降低整个CDAC所需要的单位电容数和ADC的功耗.同时采用了分离电容校正技术来降低整体CDAC的非线性和失调校正技术来降低比较器电路的失调.在0.18,mm CMOS工艺下完成了一款10-bit 10-Msample/s的电路原型设计及相应的版图设计和验证工作,带有PAD的芯片整体面积为1,2mm.芯片后仿真结果表明:该转换器在校正情况下,4.89,MHz输入信号频率下信号噪声谐波比(SFDR)为61.43,dB,比不校正提高了54%,;有效位数达到9.90,bit,比不校正提高了3.7,bit;在1.8,V电源电压下功耗仅为255.61,mW.

According to the strict requirements of the current networking technology on power consumption,a low power successive approximation register analog-to-digital converter（SAR ADC）circuit based on segmented capacitor has been designed.The capacitor array is used to reduce the number of unit capacity and power consumption of the ADC needed by the whole CDAC.At the same time,the separation capacitor calibration technique is adopted to reduce the overall CDAC nonlinear correction and the disorder technology is adopted to reduce the imbalance of the comparator circuit.A 10-bit 10-Msample/s circuit prototype design and the corresponding layout design and verification work have been completed under the 0.18,μm CMOS process,with PAD chip for the whole area is 1 mm^2.The simulation results show that when the chip converter is under the condition of correction with 4.89,MHz input signal frequency,the spurious free dynamic range（SFDR）is 61.43,dB,which is 54%, higher than without correction.The effective number of bits（ENOB） reached 9.9,bit,increased by 3.7 bit compared with that under the condition of non correction.The power consumption is only 255,mW at 1.8,V power supply.