一种减小数字时钟延时单元温漂的方法

A Method of Reducing the Delay Temperature Drift for Digital Clock Delay-Cells

介绍了一种减小数字时钟延时单元温漂的方法,利用一个具有正温度系数的带隙基准电压源Bandgap,产生参考电压V_(REF);电压缓冲器LDO接收参考电压V_(REF)并作用于延迟链;延迟链由延迟单元TAP串联而成,用来产生时钟的相位延迟。通过调整Bandgap的正温度系数,使LDO的输出电压随温度升高而升高,升高的电压会使延迟单元TAP的延时减小,从而抵消延迟单元TAP由于温度升高而增大的延时。

In the paper, a design reducing the delay temperature drift of digital clock delay-cellis described, which includes a Bandgap reference voltage （VREF） generator having a positive temperature coefficient, a LDO which receives the VREF and power the delay line. The delay line contains a series of delay-cells and used for shift the clock phase. By a positive temperature coefficient of Bandgap designed, the delay-cell power voltage will change same direction with temperature, which compensates the delay variation of delay-cell caused by the changed temperature.