应用Genus综合方案提高HDMI芯片综合质量

Using Genus Synthesis Solution to Improve Synthesis Quality for HDMI SoC

逻辑综合是集成电路设计的一个重要流程,本文讨论了应用Genus综合解决方案来改进芯片的性能、功耗、面积和与布局布线工具的相关性。传统的逻辑综合方案是通过分析负载来计算延时的,它没有考虑线延时的影响,因此逻辑综合和布局布线得到结果在性能、功耗、面积有很大的差别;新的综合方案是在综合中导入完整的布局物理信息,通过全面分析负载和线延时来计算时延,使得综合和布局布线的结果有良好的相关性。同时Genus采用全局分析来优化设计架构,能合理的分配资源,有效权衡芯片的性能、功耗、面积的取舍。在高清多媒体接口(HDMI)端口控制芯片设计实现中,我们采用Genus逻辑综合方案,获得了芯片的面积减少5%、功耗降低8%的良好结果。

Logic synthesis is a very important flow in IC design methodologies. In this paper we discusses to improve PPA（Performance Power Area）and timing correlation with post-place-and-route tools by using Genus synthesis solution. Traditional synthesis flow uses vendor-supplied wire-load models based on fanouts, which does not provide accurate wire delay information especially for designs where a significant portion of the delays are contributed by the wires. Consequently, there are relative big differences in performance, area, and power between the logic and physical designs. The synthesis with physical information flow uses a complete placement and considers congestion and legal placement as a cost function during the RTL-to-gates phase, to create a better netlist. With global analytical architecture optimization, it is possible with various PPA trade-offs. This flow ensures both the best accuracy and the most predictable closure with back-end tools. To our HDMI SOC, by Using Genus physical synthesis flowthe area is reduced about 5% and the power is reduced about 8%.