一种电流模DC-DC芯片中低延时电流比较器的设计

The Design of Current Comparator in DC-DC Regulator with Low Delay Time

文中设计了一种应用于电流模DC-DC芯片的低延时电流比较器。其主要作用是将电感的峰值电流与所需电流进行比较,输出控制信号,以达到调节输出电压的目的。利用0.35μm BCD工艺HSPICE模型参数对该电流比较器的性能进行仿真模拟,结果表明该电流比较器的功耗为100μW,延迟时间最小为11 ns,满足设计要求,并提高了芯片性能。

A novel current comparator in DC-DC regulator with low delay time is presented in this paper.Its main role is to detect the peak inductor current,compares detected peak-value current of the inductor with the designed value,and outputs control signal in order to regulate the output voltage.The simulation results by using 0.35μm BCD HSPICE models show that the consumption is under 100μW and the delay time is about 11 ns.The specifications are satisfied,and the characteristics of the chip are improved evidently.