主线实验教学法研究及其在VHDL程序设计课程中的应用

Research on the Main-line Experiment Teaching Method and Its Application to VHDL Design

现有的不少实验课程中,练习实验普遍存在着零散、不系统的缺憾。为了让同学们在有限的课程实验中更好地得到系统地训练,主线实验教学法将一系列高度系统化的实验练习衔接起来,途径各个阶段性小实验,最后完成终极实验。整个实验流程具有很强的目的性和循序渐进性,各个子项之间环环相扣,承前启后。通过在本科课程VHDL程序设计中近两年来的教学测试,与原来的传统教学方法成效相比,采用主线实验的教学方法能够大大地提高同学们学习的主动性,层层递进的阶段实验使大家一直保持着学习的动力与激情,解决问题式的实验要求又能够培养创新意识。同时,终极实验的完成也带来很强的学习成就感。

In some experiment courses, there is a common weakness that the exercise experiments are discrete and not systematic. In order to provide some systematic training for the students in the limited courses, the main-line experiment proposed in this paper is a systematic collection of a series of experiments including some phase ones and a final goal. The entire course is with a strong purpose and the items are hierarchical and connected to each other. This method has been applied to design course of VHDL （very high speed integrated circuit hardware description language ） for undergraduate students for two years. Compared to the traditional method, the main-line experiment teaching method can greatly improve student initiative, keep their motivation and passion to study, foster their innovation and bring them a very strong sense of achievement.