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3D芯片绑定中测试绑定次序对成本的影响 被引量:1

The Bonding Order's Impact on Cost During Mid-Bond Test of 3D Chip
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摘要 针对3D SICs(3D Stacked Integrated Circuits,三维堆叠集成电路)在多次绑定影响下的成本估算问题,现有的方法忽略了实际中经常发生的丢弃成本,从而使得理论的测试技术不能很好的应用于实际生产.本文根据绑定中测试的特点,提出了一种协同考虑绑定成功率与丢弃成本的3D SICs理论总成本模型.基于该模型,提出了一种3D SICs最优绑定次序的搜索算法.最后,进一步提出了减少绑定中测试次数的方法,实现了"多次绑定、一次测试",改进了传统绑定中测试"一绑一测"的方式.实验结果表明,本文提出的成本模型更贴近于实际生产现状,最优绑定次序、最优绑定中测试次数可以更加有效指导3D芯片的制造. Nowadays,due to the lack of appropriate 3D SICs( 3D Stacked Integrated Circuits) cost estimation methods under the impact of the multiple bonding,and the generally neglect of the discarding costs in test process production,the existing test methods can not be well applied in the actual production. Based on the feature of mid-bond test,this paper proposed a 3D SICs theoretical total cost model,by synergistically considering the bonding rate and discarding cost,further,a3 D SICs optimal bonding order algorithm is proposed. Finally,the paper also puts forward a method to optimize the midbonding test times. This method can achieve " multiple bondings but plus one test" by replacing the traditional " one bonding and plus one test" method. Experimental results showthat the cost of the proposed model is closer to the actual production.Optimal bonding order and Optimized mid-bonding test times can be effective to guide the 3D chip manufacturing.
出处 《电子学报》 EI CAS CSCD 北大核心 2017年第9期2263-2271,共9页 Acta Electronica Sinica
基金 国家自然科学基金重点项目(No.61432004) 国家自然科学基金(No.61474035 No.61204046 No.61306049) 安徽省科技攻关(No.1206c0805039) 安徽省自然科学基金(No.1508085QF129) 教育部新教师基金(No.20130111120030)
关键词 丢弃成本 成本模型 绑定次序 绑定中测试 测试次数优化 discarding cost cost model stacking order mid-bond test test times optimization
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  • 1戚肖宁,冯之雁,严晓浪.时延驱动的VLSI版图规划算法[J].电子学报,1995,23(2):103-105. 被引量:2
  • 2方建平,郝跃,刘红侠,李康.应用混合游程编码的SOC测试数据压缩方法[J].电子学报,2005,33(11):1973-1977. 被引量:20
  • 3J Cong, W Jie, Y Zhang. A thermal-driven floorplan for 3D-ICs [ A]. Proc. Int. Conf. Comput.-Aided Des[ C ]. San Jose, CA, USA, 2004.306 - 313.
  • 4W-L Hung,G M Link,Y Xie,N Vijaykrishnan, M J Irwin. In- terconnect and thermalaware floorplan-ning for 3D micropro- cessors[ A]. Proc. Int. Syrup. Quality of Electronic Design[ C]. San Jose,CA,USA,Mar.2006.98- 104.
  • 5P-Q Zhou, Y-C Ma, Z-Y Li, R P Dick, S Li, H Zhou, X-L Hong, Q Zhou. 3D-STAF: Scalable temperature and leakage aware floorplanning for three-dimensional integrated circuits [ A]. Proc. Int. Conf. Comput. -Aided Des [ C ]. San Jose, CA, USA, 2007.590 - 597.
  • 6X Li, Y Ma, X Hong, S Dong, J Cong. LP based white space redistribution for thermal via planning and performance opti- mization in 3D ICs[ A]. Proc. Asia South Pacific Des. Autom. Conf[ C]. Seoul, Korea, 2008.209 - 212.
  • 7Yun Huang, Qiang Zhou, Yici Cai.A thermal-driven force-di- rected floorplan-ning algorithm for 3D ICs[ A]. International Conference on Computer Aided Design and Computer Graph- ics[ C]. Huangshan, China, 2009.497 - 502.
  • 8B Goplen, S Sapatnekar. Efficient thermal placement of stan- dard cells in 3D ICs using a force directed approach [A ]. Proc. Int. Conf. Comput.-Aided Des [ C ]. San Jose, CA, USA. ,Nov.2003.86- 90.
  • 9J Li,H Miyashita.Post-placement thermal via planning for 3D integrated circuit [ A ]. Proc. Asia Pacific Conf. Circuits Syst C]. Singapore, 2006.808 - 811.
  • 10J Cong, G-J Luo, J Wei, Y Zlaang. Thermal-aware 3D IC placement via transformation [ A ]. Proc. Asia South Pacific Des. Autom. Conf[ C]. Yokoha-ma, Japan, 2007.780 - 785.

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