摘要
This paper presents a power-efficient 100-MS/s,10-bit asynchronous successive approximation register（SAR） ADC.It includes an on-chip reference buffer and the total power dissipation is 6.8 mW.To achieve high performance with high power-efficiency in the proposed ADC,bootstrapped switch,redundancy,set-and-down switching approach,dynamic comparator and dynamic logic techniques are employed.The prototype was fabricated using 65 nm standard CMOS technology.At a 1.2-V supply and 100 MS/s,the ADC achieves an SNDR of 56.2 dB and a SFDR of 65.1 dB.The ADC core consumes only 3.1 mW,resulting in a figure of merit（FOM） of 30.27 fJ/conversionstep and occupies an active area of only 0.009 mm^2.
This paper presents a power-efficient 100-MS/s,10-bit asynchronous successive approximation register（SAR） ADC.It includes an on-chip reference buffer and the total power dissipation is 6.8 mW.To achieve high performance with high power-efficiency in the proposed ADC,bootstrapped switch,redundancy,set-and-down switching approach,dynamic comparator and dynamic logic techniques are employed.The prototype was fabricated using 65 nm standard CMOS technology.At a 1.2-V supply and 100 MS/s,the ADC achieves an SNDR of 56.2 dB and a SFDR of 65.1 dB.The ADC core consumes only 3.1 mW,resulting in a figure of merit（FOM） of 30.27 fJ/conversionstep and occupies an active area of only 0.009 mm^2.
