期刊文献+

一种用于ESD保护的SCR触发电路

A SCR Trigger Circuit for ESD Protection
下载PDF
导出
摘要 介绍一种检测ESD电压并输出触发或关断信号的电路结构。通过对ESD脉冲的上升沿进行分辨,然后输出触发信号从而触发SCR钳位器件对内部电路进行保护,并在ESD脉冲结束时对脉冲下降沿进行检测,从而输出关断信号关断SCR钳位器件,防止闩锁效应的发生。仿真结果显示,该电路能较好地检测ESD脉冲的上升沿或下降沿而输出不同的信号,从而能降低SCR钳位器件的触发电压,并防止闩锁效应。 The paper describes a new SCR triggering circuit for ESD protection. It can detect the ESD voltage and output a triggering signal and open the SCR device to protect the inner circuit. After the ESD case, the circuit can detect the fall edge of ESD voltage to output a signal. Then the SCR device will be turned off to prevent latch-up effect. The simulation results show the novel triggering circuit can detect the ESD pulse and output different signals, so it is good for reducing the triggering voltage SCR and preventing latch-up effect.
出处 《电子与封装》 2017年第10期26-30,共5页 Electronics & Packaging
关键词 ESD防护 触发电路 触发电压 闩锁效应 ESD protection triggering circuit triggering voltage latch-up effect
  • 相关文献

参考文献3

二级参考文献20

  • 1杜鸣,郝跃.CMOS工艺中栅耦合ESD保护电路[J].西安电子科技大学学报,2006,33(4):547-549. 被引量:6
  • 2Ker M D. Whole-chip ESD Protection Design with Efficient VDD-to-VSS ESD Clamp Circuits for Submieron CMOS VLSI[J]. IEEE Trans on Electronic Devices, 1999, 46(1): 173-183.
  • 3Andrea C, Simone G, Augusto T, et al. Electrostatic Discharge Effects in Ultrathin Gate Oxide MOSFETs[J]. IEEE Trans on Devices and Materials Reliability, 2006, 6(1):87-94.
  • 4Smith J C, Boselli G. A MOSFET Power supply clamp with feedback enhanced triggering for ESD protection in advanced CMOS technologies [J]. Microelectronics Reliability, 2005, 45(2): 201-202.
  • 5Ker M D, Chen J H. Self-Substrate-Triggered Technique to Enhance Turn-On Uniformity of multi-Finger ESD Protection Devices [J]. IEEE Solid-State Circuit, 2006, 41(11) :2601-2609.
  • 6Ker M D, Lin K H. The Impact of Low-holding-voltage Issue in High-voltage CMOS Technology and Design of Latchup- free Power-rail ESD Clamp Circuit for LCD Driver IC [J]. IEEE Solid-State Circuit, 2005, 40(8) :1751-1759.
  • 7Chou H M, Lee J W, Li P Y. A Floating Gate Design for ESD Protection Circuits[J]. The VLSI Journal, 2007, 40(2):161-166.
  • 8Feng Haiqiang, Chen Guang, Zhan Rouying, et al. A Mixed-mode ESD Protection Circuits Simulation-design Methodology [J]. IEEE Solid-State Circuit, 200a, 38(6): 995-1006.
  • 9Ker M D, Chang W J. ESD Protection Design with On-chip ESD Bus and High-voltage-tolerant ESD Clamp Circuit for Mixed-voltage I/O Buffers [J]. IEEE Solid-State Circuit, 2008, 55(6): 1409-1416.
  • 10Malobabic S, Ellis D F, Salcedo J A, et al. Gate oxide evaluation under very fast transmission line pulse (VFTLP) CDM-type stress [C]. Proceedings of the 7th International Carribbean Conference on Devices, Circuits and Systems, Mexico, 2008 : 1-8.

共引文献14

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部