基于SystemVerilog的同步FIFO的验证平台搭建

Verification Platform of Synchronous FIFO Based on SystemVerilog

针对于传统验证平台利用Verilog搭建的验证平台效率低,准确度低的局限性,提出了一种基于SystemVerilog系统级语言的验证平台建模方法,可以有效地降低复杂度和设计风险。由于FIFO在大多数工程中利用率极高,也极易出现问题,通过对FIFO模块进行验证平台建模,可以有效地降低设计与验证的时序竞争风险,实现验证平台的复用和验证过程中的自动监测,并且在搭建验证平台的过程中阐述了基本的验证流程,以及结合System Verilog语言介绍了一些基本建模规则和技巧。

This paper mainly introduces the practical verification environment of synchronous FIFO based on System Verilog structures,which breaks through the traditional limitations in verification platform modeling,can greatly improve the efficiency of chip test and interface protocol,and can effectively reduce the risk of design. The FIFO verification platform in this paper can effectively reduce the risk of the time sequence competition between design and verification,realize verification platform reuse and automatic monitoring in verification process. The paper also describes basic verification process,and introduces some of basic rules and modeling skills combined with System Verilog language in the process of building verification platform.