摘要
为提高权电容阵列DAC的性能,本文通过建立权电容阵列DAC的理想模型和状态转换模型,求解出零状态输出和非零状态输出,证明了权电容阵列DAC输出仅包含系统的零状态响应,而与前次输入无关.根据权电容阵列DAC的频率响应特性和时域响应函数,得到一种电容阵列DAC转换速度的估计方法,并建立了支路时间常数与转换开关导通电阻之间的限制关系.通过仿真分析验证了权电容阵列DAC转换速度的估计方法,为权电容阵列DAC的设计和应用提供了理论依据.
In order to improve the performance of weighted capacitor array DAC(Digital to Analog Converter),the output function on zero condition and non-zero condition is found out through building up ideal model and state transition model of weighted capacitor array DAC.It proves the output of weighted capacitor array DAC only includes zero condition,and no relate with input.According to the frequency respond and timing respond function,a method of weighted capacitor array DAC transition rate estimation and correlation between sub-circuit RC factor and switching resistor are built up.Detail simulation results are shown in this paper to verify the method of weighted capacitor array DAC transition rate estimation.It provides the theory foundation for the application of weighted capacitor array DAC.
出处
《北京交通大学学报》
CAS
CSCD
北大核心
2017年第2期79-84,共6页
JOURNAL OF BEIJING JIAOTONG UNIVERSITY
基金
国家自然科学基金(61273061)~~
关键词
数模转换器
权电容阵列
转换速度
digital to analog converter
weighted capacitor array
transition rate