基于FPGA的进位存储大数乘法器的改进与实现

Improvement and implementation of carry-save large numbers multiplication on FPGA

提出了一种基于FPGA的进位存储的大数乘法器的改进算法,该算法采用串并混合结构可以在一个时钟内完成多次迭代计算,减少了完成一次运算的时钟数,因此有效地提高了大数乘法器的速度。最后硬件结构设计在Altera Stratix Ⅱ EP2S90F1508C3上实现,给出了192位、256位以及384位的乘法器性能分析,其中,192位可达到0.18μs,256位达到0.27μs,384位达到0.59μs,速度上都提高了3.5倍左右。

This paper proposes an improved algorithm of carry-save large numbers multiplication on FPGA, which can complete multiple iterations of operation in a clock with a serial-parallel hybrid structure. To some extent, reducing clocks to complete a operation, the structure improves the speed of the large numbers multiplication effectively. Finally, the results of the implementation of this multiplier for several operands sizes（192 bit, 256 bit, 384 bit）on Altera Stratix Ⅱ EP2S90F1508C3 show that the time of 192 bit is 0.185 microsecond, 256 bit is 0.271 microsecond, and 384 bit is 0.595 microsecond. As a result, the paper’s design is about 3.5 times than the previous design in speed.