基于FPGA的改进ADS-B纠错算法设计与实现

Design and implementation of improved correction algorithm for ADS-B based on FPGA

基于S模式数据链技术的广播式自动相关监视(ADS-B)系统,凭借其建设成本低及其精度高的优点而广泛用于空中交通管制等领域。然而,ADS-B系统的广播性和信号非加密特点,在高A/C应答异步干扰(FRUIT)交叠的情况下,使得信号在接收端被接收时极易产生误码。针对这一问题,结合FPGA的并行运算特性与资源配置情况,在循环冗余编码(CRC)校验和置信度判定的基础上,提出了一种基于FPGA的改进ADS-B纠错算法。给出了该改进算法的设计方案,并通过FPGA平台进行了大量实采信号的测试验证。经多次测试的结果表明:在不影响纠错性能的条件下,该改进算法可节省硬件开销,提升信号处理速度,保证了信号传输的可靠性。

ADS-B （automatic dependent surveillance broadcast） system is based on Mode S data link, which is widely used in the field of air traffic management owing to its low cost and high precision. However, ADS-B is vulnerable to interference. The very severe overlapping Mode A/C False FRUIT （replies unsynchronized to interrogator transmission） environment leads to bit errors of ADS-B signal. In order to solve this problem, an improved signal correction method is presented combining with serial operation characteristics and resource allocation of FPGA, CRC （cyclic redundancy check） and bit confidence for ADS-B signal. This method is designed and tested by FPGA platform. ADS-B signal test results of FPGA platform show that this improved method needs less hardware consumption and can improve signal processing speed without affecting the performance of error correction, ensuring the transmission reliability of ADS-B signal and making correction rate reaches 100%.