一种伪差分两级环形振荡器的设计

Design of a Pseudo-Differential Two Stage Ring Oscillator

设计了一种伪差分两级环形振荡器,可为锁相环提供8GHz四相位正交时钟。通过分析耦合两级环形振荡线性模型,对四级环形振荡结构进行优化,提出了伪差分两级环形振荡结构。基于单级缓冲器的开环分析,可对振荡器的输出频率进行精准估算,并判断振荡情况。采用65nm CMOS工艺进行设计与仿真。结果表明,在1.2V电压下,振荡器的功耗为6.9mW,1 MHz频率处的相位噪声为-82.104 5dB,满足高速SerDes接口的设计要求。

A pseudo-differential two stage ring oscillator was designed to provide an 8 GHz four phase quadrature clock signal for phase-locked loop.By analyzing the coupled two stage ring oscillating linear model,the four stage ring oscillating structure was optimized,and a pseudo-differential two stage ring oscillating structure was presented.The proposed analysis offered a precise prediction on the oscillator behavior such as an output frequency and whether or not oscillating,based on an open-loop approach with a single stage buffer.The circuit was designed and simulated in a 65 nm CMOS process.Simulation results showed that the voltage controlled oscillator dissipated 6.9 mW from a 1.2 Vsupply.The measured phase noise at 1 MHz frequency was-82.104 5 dB,which had met the design requirements of high speed SerDes interfaces.