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一种电场调制载流子存储槽栅双极型晶体管 被引量:1

An Electric Field Modulation Carrier Storage Trench Bipolar Transistor
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摘要 提出了一种性能优良的电场调制载流子存储槽栅双极型晶体管(CSTBT)。结合电场调制原理,在器件的载流子存储(CS)层引入P掺杂条,改善器件栅极下方氧化硅拐角处的电场分布,防止器件提前发生雪崩击穿,提高了器件的击穿电压。器件处于关断状态时,内部大量的空穴载流子通过CS层中未完全耗尽的P掺杂条到达发射极,抑制了CS层阻挡空穴的作用,有效提高了器件的关断速度。与传统CSTBT器件相比,改进器件的击穿电压值提高了379V,关断时间缩短了19.1%,器件性能大幅提高。 Carrier storage trench bipolar transistor(CSTBT)with electric-field modulation for high performance was proposed.Guided under the electric field modulation principle,the P-pillars were inserted into the carrier storage(CS)layer,which could modify the electric field distribution at the corner of silicon oxide below the gate electrode,preventing the avalanche breakdown in advance and improving the breakdown voltage of the device.When the device was turned off,a large number of internal hole carriers could reach the emitter through the P-pillars which were not fully depleted in the CS layer.Then the hole-blocked effect of the CS layer could be suppressed,which had effectively improved the turn-off speed of the device.Compared with conventional CSTBT,the proposed structure increased the breakdown voltage by 379 Vand shortened the turn-off time by 19.1%.The performances of the device had been improved greatly.
作者 杨大力 汪志刚 樊冬冬 YANG Dali WANG Zhigang FAN Dongdong(MCU Joint Lab. , School of Information Science and Technology , Southwest Jiaotong University, Chengdu 610031, P. R. China)
出处 《微电子学》 CSCD 北大核心 2017年第5期710-713,717,共5页 Microelectronics
基金 国家自然科学基金资助项目(61404110)
关键词 载流子存储槽栅双极型晶体管 电场调制 电场分布 击穿电压 关断时间 CSTBT Electric field modulation Electric field distribution Breakdown voltage Turn off time
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  • 1陈星弼.功率MOSFET和高压集成电路[M].南京:东南大学出版社,1990..
  • 2ZENG J,MAWBY P A, TOWERS M S, et al. Design of IGBTs for latch-up free operation [J]. Sol Sta Elec, 1994, 37(8): 1471-1475.
  • 3RUSSELL J P, GOODMAN A M, GOODMAN L A, et al. The COMFET-a new high conductance MOS-gated device[J]. IEEE Elec Dev Lett, 1983, 4(3) : 63-65.
  • 4BALIGA B J,ADLER M S, GRAY P V, et al. Suppressing latch up in insulated gate transistors [J]. IEEE Elec Dev Lett, 1984, 5(8) : 323-325.
  • 5NARESH T, BALIGA B J. A new IGBT structure with a wider safe operating area(SOA) [C] // IEEE Int Symp Power Semicond Dev & ICs. 1994: 177-182.
  • 6AKIO N, HIROMICHI O, MAMORU K, et al. Nonlatch-up 1200 V 75 A bipolar-mode MOSFET with large ASO [C]// Int Elec Dev Meet. 1984: 860-861.
  • 7YILIMAZ H. Cell geometry effect on IGBT latch-up [J]. Elec Dev Lett, 1985, 6(8) 419-421.
  • 8TRIVEDI M, SHENAI K. IGBT dynamics for clamped inductive switching[J]. IEEE Trans Elec Dev, 1998, 45 (12) : 2537-2545.
  • 9SHEN Z J, ROBB S P. Design and modeling of the 600 V IGBT with emitter ballast resistor [C]// 53rd Ann Device Research Conf. 1995: 108-109.
  • 10YUN C, KIM S, KWON Y, et al. High performance 1200 V PT IGBT with improved short-circuit immunity [C]//Proc 10th Int Symp Power Semicond Dev and ICs. 1998: 262-264.

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