一种应用于指令级并行处理器的低功耗并行度调整方案（英文）

A Parallelism Tuning Scheme to Reduce Static Energy for ILP Processors

对于指令级并行处理器(ILP,instruction level parallelism),在执行不同应用程式时,硬件资源的需求量差异很大,甚至在同一支程式中也是如此,某些空闲的硬件资源会产生额外的静态能量,提出重新设置应用程式中不同区块的执行并行度,把空闲的硬件资源关断来降低静态能量的方案,利用Core Mark Pro的标准测试集中的应用程式进行测试,静态能量降低超过40%且执行时间增加少于10%.

For instruction-level parallelism（ILP） processors, the requirement of hardware resources changes between applications, even within an application. Some unused hardware resources will result in unexpected static energy. The scheme, which is to tune parallelism for different portions within an application to turn off idle hardware resources, is proposed. The proposed algorithm could save more static energy with meeting the requirement of users. The experimental results of evaluation with Core Mark Pro benchmark suits show the execution energy could be reduced more than 40% and the execution time just increases less than 10%.