基于PRBS检测的8B/10B编码器设计

Design of 8B/10B encoder based on PRBS test

基于减少8B/10B编码器占用的逻辑资源和保证该编码器误码率为0的目的,采用查表法和组合逻辑实现相结合的方法设计实现了符合嵌入式互连规范RapidIO协议的8B/10B编码器,通过伪随机二进制序列(Pseudo Random Binary Sequence,PRBS)检测方法对该编码器进行验证。FPGA综合结果表明,该设计占用的LUT为32,占用较少的逻辑资源。采用PRBS-7测试结果表明,该8B/10B编码电路误码率为0,表明了该8B/10B编码器传输信息的可靠性。

Based on the purpose of reducing the occupation of logic resources of the 8B/10B encoder and ensuring the bit error rate is O, the design uses the method of combination of look-up table method and combinatory logic implementation method implements the 8B/lOB encoder which agrees the RapidIOpro- tocol and uses PRBS to verify the 8B/lOB encoder. FPGA comprehensive results show that the design occupies 32 of LUTs which are few logic resources, the result of PRBS-7 test shows that the 8B/10B encod- er bit error rate is 0, indicates that the information transmission of the 8B/10B encoder is reliable.