一种用于产生高频八相位时钟的延时锁定环

A delay-locked loop for generating high speed eight phases clock

针对传统延时锁定环工作频率低、锁定范围窄的问题,设计了一种可产生高频宽范围八相位时钟的延时锁定环。设计一种仅由8个MOS管构成的高频鉴相器,这种高频鉴相器无传统鉴相器的复位端,可减小死区并降低抖动;采用差分串联电压开关逻辑作为压控延时单元,以满足宽范围延时的要求,并通过电阻矫正的方法解决其上升、下降沿延时不匹配的问题;采用旁路控制单元对压控延时线进行二次调节,增大延时范围的同时解决了失锁和谐波锁定的问题。基于SMIC0.18μm CMOS工艺和1.8V电源电压进行仿真,实现了一种用于产生高频八相位时钟的延时锁定环,芯片核心尺寸为0.03mm2,锁定工作频率为1.8~4.5GHz,在输入参考时钟为4.5GHz下,抖动为3.2ps,功耗为54mW。

In order to conquer the weakness of low operation frequency and narrow lock range of the conventional DLL,a delay-locked loop（DLL）for generating high speed eight phases clock is implemented.A high frequency phase frequency detector（PFD）with eight transistors is proposed.It decreases jitter and dead zone by not using reset path.Fast differential cascode voltage-switch-logic（DCVSL）-based voltage control delay cell is adopted to satisfy requirement of wide range delay for solving mismatch of rising delay and falling delay through resistance correction.A shunt control element is employed to fulfil the second time control of voltage control delay line（VCDL）,expands operation frequency and solves false lock as well as harmonic lock.The proposed DLL,which is capable of generating eight phases clock,is implemented in SMIC 0.18μm CMOS process,a chip area is 0.03 mm2,a reference frequency range is 1.8-4.5 GHz.At maximum input frequency,the proposed DLL has a jitter of 3.2 ps and dissipates 54 mW power.