基于DSP Builder的16阶FIR低通滤波器设计

Design of 16-order FIR Low-pass Filter Based on DSP Builder

通过对语音信号特性进行分析,利用传统的数字处理方法进行算法推导,以Quartus Ⅱ、Matlab/simulink软件为基础,用Verilog HDL语言来实现FIR数字滤波器的仿真,并对DSP Builder和FPGA所设计出的FIR低通滤波器功能进行比较、仿真和分析,通过仿真结果验证该方案的可行性,对于以后FPGA滤波器的实现,具有一定的参考应用价值。

Based on the Quartus II and Matlab / simulink software, the Verilog HDL language is used to realize the simulation of FIR digital filter, and the DSP tool and FPGA are used to analyze the characteristics of the speech signal. The traditional digital processing method is used to derive the algorithm. The performance of the FIR low-pass filter is compared, simulated and anal-yzed. The feasibility of the scheme is verified by the simulation results. It has some reference value for the implementation of the FPGA filter.