支持指令预取的两级指令缓存WCET分析

Two-level instruction cache WCET analysis with instruction prefetching

随着嵌入式实时系统中硬件的不断发展,许多处理器具有两级指令缓存并且支持指令预取技术.指令预取技术能否在两级指令缓存结构中广泛应用,取决于两级指令缓存下支持指令预取的缓存最坏情况执行时间(WCET,Worst-Case Execution Time)能否被分析.目前虽然存在一些支持指令预取的缓存分析方法,但是它们都只能用于单层指令缓存,并不能用于多层组关联指令缓存WCET分析.通过扩展在两级指令缓存架构下缓存分析的支持指令预取的抽象语义,本文提出了基于抽象解释的支持指令预取的缓存WCET分析方法.本文分析指令预取对于L1指令缓存和L2指令缓存访存延迟和抽象缓存状态的影响,设计了支持指令预取的L1指令缓存和L2指令缓存访存延迟计算方法和缓存状态分析算法.本文实验中对不同的Benchmarks进行了分析,结果表明本文的支持指令预取的缓存WCET分析方法是有效的,在不同的指令预取度下,指令预取比没有指令预取的最坏情况下平均提升了19.3%的性能.

With the development of hardware in embedded real-time systems,a lot of processors have two-level instruction cache architecture and support instruction prefetching technology.The instruction prefetching can be widely applied in two-level instruction cache only the instruction cache WCET(Worst-Case Execution Time) with instruction prefetching can be analyzed.Although the cache analysis methods with instruction prefetching have already existed,but the researches are limited on the single-level instruction cache and they cannot be applied on the multi-level set-based instruction cache WCET analysis.Through extending the abstract semantics of the instruction cache analysis with the instruction prefetching under the two-level instruction cache architecture,this paper proposes instruction cache WCET analysis method with instruction prefetching based on abstract interpretation.This paper analyzes the effect of instruction prefetching on the cache access latency and abstract cache state for L1 and L2 instruction cache,and then designs the cache access latency computation method and the cache state analysis algorithm with instruction prefetching.The different benchmarks is analyzed in experiment,and the result shows that our cache WCET analysis method with instruction prefetching is effective,and instruction prefetching can improve the worst-case performance on an average 19.3% than that of without instruction prefetching under the different prefetching degrees.