一种1553B总线控制器与处理器的接口设计方法

A Design Method of 1553B Interface Between ACE and Processor

1553B总线控制器(ACE)通过不同的硬件配置工作于不同模式。8/16位缓冲零等待/非零等待是最常用的工作模式。每种模式的硬件设计、软件读写访问时序各不相同。这些不同在工程设计中易被忽视,从而造成设计错误。分析了不同模式的读写时序,指出了不同模式硬件设计的不同,给出了ACE的8/16位缓冲零等待/非零等待模式的硬件设计。在此基础上,分别基于单片机、DSP,设计了ACE不同模式下的硬件接口电路。对使用1553B总线的设计人员、测试人员有一定的指导意义。

MIL-STD-1553 B ACE can be set as several modes by different hardware connection. 8/16 bit buffered＂zero wait＂/＂non-zero wait＂are commonly used. Hardware design and read-write timing is different for every mode. These differences were neglected usually so that design was fallibly. Read-write timing analysis was done,distinctness of hardware design for every mode was pointed out,hardware design of 8/16 bit buffered ＂ zero wait＂/＂ non-zero wait＂ was presented.Hardware connection design of 1553 B ACE with DSP and single chip was given. This article is meaningful to designer and tester who are using 1553 B Bus.