PCIe接口的BAC时统节点设计

Design of BAC Time Node for PCIe Interface

针对BAC时统节点在PCIe计算机系统中的应用,基于新型线性隔离和PCIe端点硬核应用和BAC码转换解析,实现了一种BAC时统节点设计;实现了该节点的总体电路设计,同时实现了BAC输入信号的线性隔离电路、迟滞比较输出BAC信号采样点电路、BAC信号的A/D转换采集电路、ALTERA FPGA的FIFO和PCIe端点硬核应用设计;基于FPGA实现的PCIe接口、FIFO和控制逻辑计以及实现的线性隔离,在简化节点设计的同时,也大大提高了适用性。

In view of the application about BAC time node in the PCIe computer system, Based on the PCIe endpoint hard core and BAC conversion with code parsing , a BAC time node design is implemented. The overall circuit of the node is realized, which is including BAC input signal linear isolation circuit, hysteresis comparison output circuit for BAC signal sampling , and A / D conversion acquisition circuit. FIFO storage and PCIe endpoint are also realized based on ALTERA FPGA. The node has simple composition and Good applicability through linear isolation and FPGA integration design about PCIe, FIFO and control logic.