基于FPGA的高效FIR滤波器设计

Design of efficient FIR filter based on FPGA

为了有效提高数字信号处理的实时性,文中利用多相分解法推导了快速FIR滤波器的一种高效实现算法,通过Matlab,Quartus II软件的仿真和测试验证了设计的可行性。结果表明:该滤波器运行速度基本上是直接实现的2倍,运算量比直接实现要少25%左右,工作效率要比直接实现提高了大约50%。整个设计过程由软件实现,参数易于修改,具有较大的实用性。

In order to effectively improve the real - time performance of digital signal processing, an efficient algorithm for fast FIR filter is derived using polyphase decomposition method. The feasibility of the design was verified by simulation and test with Matlab and QuartusII software. The results show that the filter is almost twice as fast as the direct one. The computation burden is about 2 5 % less than the direct implementation. The efficiency of work is about 5 0 % higher than the direct im-plementation. The entire design process is implemented by software, and parameters are easy to modify. It has great practicability.