基于65 nm CMOS工艺的D波段功率放大器设计

Design of D-band 65 nm CMOS Power Amplifier

基于65 nm CMOS工艺,研究和设计了一款四级全差分结构的D波段功率放大器芯片.采用交叉耦合电容中和技术抵消了硅基CMOS晶体管栅漏寄生电容,提高了放大器的增益和稳定性.通过优化输入输出巴伦和级间变压器,功率放大器的增益和输出功率得到了显著改善.仿真结果显示,在1.2V的电源电压下,工作在140GHz的功率放大器的功率增益为16.7dB,饱和输出功率为11.3dBm,输出1dB压缩点为7.0dBm,功耗为130mW.芯片面积为500μm×455μm.

This paper presents a four-stage fully differential D-band power amplifier in 65 nm CMOS technology.Cross-coupled capacitors are adopted to neutralize the gate-drain parasitic capacitance of silicon-based CMOS transistor,which improves the gain and stability of the amplifier.By optimizing the Balun and inter-stage transformers,this power amplifier achieves a better power gain and output power.The post-layout simulation results show that the power amplifier achieves a power gain of16.7 dB,saturated output power of 11.3 dBm,1 dB compression point of 7.0 dBm and power consumption of 130 mW at 140 GHz from a power supply of 1.2 V.The power amplifier occupies a chip area of 500μm×455μm.