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PCIE3.0接口的SSD硬盘的FPGA实现

Design of High-speed Solid State Drive in FPGA
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摘要 设计并实现了一个高性能固态盘的硬件原型系统.该固态盘以NAND闪存为存储介质,满足ONFI4.0相关标准.与主机通过第三代PCIe总线接口进行通信.主控部分基于FPGA实现.在实现上,采用了双总线结构,PCIE3.0接口并介绍了NAND闪存转换层的设计. A high-performance solid state drive（SSD） is designed and implemented in the essay. NAND flash chip that obey the standard of ONFI4. 0 is used as the storage meida in SSD. SSD communicate with the host through PCIE bus. The control part is implemented based on FPGA. A dual-bus structure and PCIE3. 0 IP core are introduced. NAND flash translation layer（FTL） is also described in detail.
作者 宋鹏程 张春
机构地区 清华大学微电子所
出处 《微电子学与计算机》 CSCD 北大核心 2017年第12期63-66,73,共5页 Microelectronics & Computer
基金 国家高新技术研究发展计划(2015AA016701)
关键词 固态盘 闪存 现场可编程逻辑门阵列 高速互联总线 solid state drive NAND flash FPGA PCI express
分类号 TN4 [电子电信—微电子学与固体电子学]
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  • 1Flynn D, Thatcher J. Apparatus, system, and method for a virtual storage layer: USA, 0011340 [P]. 2012- 01-12.
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  • 3LeeSW, ParkDJ, ChungTS, et al. Alog buffer- based flash translation layer using fully-associative sec- tor translation [J]. ACM Trans Embed Comput Syst, 2007, 6(3): article No. 18.
  • 4Gupta A, Kim Y, Urgaonkar B. DFTL: a flash trans- lation layer employing demand-based selective caching of page-level address mappings [J]. ACM SIGARCH Comput Architect News, 2009, 44(3): 229-240.
  • 5JungM, Kandemir M. An evaluation of different page allocation strategies on high-speed SSDs [C]// 4th USENIX conference on Hot Topics in Storage and File Systems. Boston, USA, 2012: article No. 9.
  • 6Hu Yang, Jiang Hong, Feng Dan, et al. Performance impact and interplay of SSD parallelism through ad- vanced commands, allocation strategy and data granu- larity [C]//International Conference on Supercomput- ing. Tucson, USA, 2011.- 96-107.
  • 7Micron. MT29F16G08ABABAM62B3WC1. [EB/OL]. [2014-01-25]. https://www, micron, com/parts/nand- flash/mass-storage/mt29f16g08ababam62 b3wcl.
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微电子学与计算机
2017年 第12期

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