低温烧结制度对ZnO-Bi2O3基压敏陶瓷显微结构与电性能的影响

Influence of Low Temperature Sintering Regimes on the Microstructure and Electrical Properties of ZnO-Bi_2O_3 Based Varistors

采用传统电子陶瓷的制备工艺,制备了相同Bi_2O_3含量、Sb_2O_3/Bi_2O_3比分别为0.25、0.50的ZnO-Bi_2O_3基压敏陶瓷,研究在800℃-950℃区间内一步烧结与两步烧结制度对陶瓷的显微结构与电性能的影响。显微结构分析表明,烧结过程中足够的Bi_2O_3液相有利于烧结,而且能够促进晶粒内含反演边界(Inversion Boundary)的ZnO晶粒的长大。烧成的样品具有发育良好的显微结构:高的致密度、均匀的含Bi第二相分布以及粒径,而且电性能良好:压敏电压327-670 V/mm,非线性系数20-31,漏电流低于0.5μA。Sb_2O_3含量较高的样品,晶粒尺寸较小,压敏电压和非线性系数较大,漏电流较小。研究还发现,ZnO晶粒尺寸以受两步烧结制度里占主要的烧结过程的影响为主。研究结果表明:与传统的1000℃以上烧结相比,合理的配方是保证在800℃-950℃区间内烧结获得综合性能良好的压敏陶瓷样品的关键。

By traditional ceramic processing method, ZnO-based varistor ceramics with the same amount of Bi_2O_3 and Sb_2O_3/Bi_2O_3=0.25, 0.50 mared as LC1 and LC2 respectively were prepared. They were sintered by a traditional one stage or two-stage regimes in the temperature range of 800 ℃-950 ℃. Microstructural analysis results confirmed that the presence of rich-Bi_2O_3-based liquid phase was good for sintering, and could also promote the grain growth with the inversion boundaries（IB） inside the ZnO grains formed by Sb_2O_3. The samples had a proper density, homogeneous distribution of Bi_2O_3-rich secondary phase and grain size. The samples possessed good properties with breakdown voltages Eb in the range of 327 V/mm-670 V/mm, nonlinear coefficient α 20 to 31, and leakage current IL lower than 0.5 μA. LC2 have a smaller average grain size, higher Eb and α, and a lower IL than LC1. Results also confirmed that the temperature of the main sintering stage played the main role in influencing the average grain size. Conclusions were given that a suitable composition enables the proper microstructure development and good current-voltage characteristics of the varistors in the temperature range of 800 ℃-950 ℃.