一种万兆以太网交换机时钟系统的设计

On Designing of a Clock System for the 10 Gigabit Ethernet switch

本文针对万兆以太网交换机设计了一种时钟系统,介绍了以太网交换机的基本组成,通过AD9517芯片进行时钟硬件的设计,以及使用FPGA开展软件设计。

This paper illustrates the design of a Clock System for the 10 GEthernet switches.It gives a brief introduction to the basic components of Ethernet switches in principle,and analyzes how to design the clock hardware by using AD9517 chip,as well as how to carry out the software design with FPGA.