基于有限状态机的高速串口通信收发器的FPGA设计

FPGA DESIGN FOR HIGH SPEED SERIAL COMMUNICATION TRANSCEIVER BASED ON FINITE STATE MACHINE

针对在多任务操作系统环境下串口通信实时性和高速性受到影响的问题,提出一种基于有限状态机的高速串口通信收发器的FPGA实现方法。串口通信收发器由波特率发生器、发送模块、接收模块和控制与状态四个模块构成,波特率发生器使用锁相环对输入时钟进行倍频和分频;接收模块和发送模块分别使用一个四状态和两状态的有限状态机实现。仿真和实测结果表明,设计的FPGA串口收发器模块电路工作稳定,速度可以达到3 Mbit/s。由于FPGA的高度并行性和有限状态机的稳定性,使用有限状态机实现的FPGA高速串口通信收发器在工业应用中能保证高速串行通信的实时性和可靠性。

Under the environment of multitask operating system, the character of real-time and high speed of serial communication is significantly affected. This article puts forward an FPGA implementation method of high speed serial communication transceiver based on finite state machine. The serial communication transceiver consists of four modules, baud rate generator, transmission module, reception module and control and status module. The baud rate generator uses a phase-locked loop to multiply and divide the input clock. The reception module and the transmission module use a finite state machine of four states and two states, respectively. Simulation and experimental results show that the FPGA serial transceiver module circuit works stably with the speed up to 3 Mbit/s. Due to the high parallelism of FPGA and the stability of finite state machine, the FPGA high speed serial communication transceiver based on finite state machine can guarantee the real-time and reliability of high speed serial communication in industrial applications.