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一种多进制LDPC编译码器硬件的实现方法 被引量:3

A Hardware Implementation Method of Encoding and Decoding Non-binary LDPC Codes
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摘要 多进制LDPC码比二进制LDPC码性能更加优异,但编译码算法较为复杂,近几年针对复杂的校验节点的更新计算多位学者提出了多种改进算法。提出基于查表法实现直接编码算法,以TMM译码算法为基础,对其译码性能进行Matlab仿真验证,基于硬件实现提出多个关键模块的优化设计方案,最终实现的编译码器资源消耗小、吞吐量大。应用结果表明,该方法实现的编译码器性能与仿真结果一致,设计方案正确、可行。 Non-binary LDPC codes have better performance than binary LDPC codes. And because of the complexity of non-binaryLDPC codes encoding and decoding algorithms,several scholars proposed some advanced methods in check node processing. The method of direct encoding algorithm based on the lock-up table is proposed. The performance of TMM decoding algorithm is verified according Matlab simulation. And some major module improved design schemes in the hardware implementation are proposed. The encoder and decoder realized in the paper need less resource and have high throughput. According to the application result,the performance of the encoder and decoder using the method is the same with simulation and the design schemes are correct and feasible.
出处 《无线电工程》 2018年第1期72-79,共8页 Radio Engineering
基金 国家自然科学基金资助项目(91638203)
关键词 多进制低密度奇偶校验 查表法 TMM译码算法 现场可编程门阵列 non-binary LDPC lock-up table method TMM decoding algorithm FPGA
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