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栅侧壁隔离层对45 nm NOR闪存栅极干扰的影响

Influence of Sidewall Spacer on Gate Disturb of 45 nm NOR Flash
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摘要 为了研究侧壁隔离层对闪存器件可靠性的影响,分别制备了Si_3N_4和SiO_2-Si_3N_4-SiO_2-Si_3N_4(ONON)复合层作为栅侧壁隔离层的45 nm或非闪存(NOR flash)器件,对编程后、循环擦写后的闪存器进行栅极干扰的测试,讨论了不同栅侧壁隔离层对栅极干扰的影响。结果表明,虽然纯氧化硅隔离层可减少NOR自对准接触孔(SAC)刻蚀时对侧壁隔离层的损伤,但其在栅极干扰时在氧化物-氮化物-氧化物(ONO)处有更高的电场,从而在栅干扰后阈值电压变化较大,且由于在擦写操作过程中会陷入电荷,这些电荷在大的栅极电压和长时间的栅干扰作用下均会对闪存器的可靠性产生负面的影响。ONON隔离层的闪存器无可靠性失效。因此以ONON作为侧壁隔离层比以纯氮化硅作为侧壁隔离层的闪存器件具有更好的栅干扰性能。 To study the effect of sidewall spacer on the reliability of flash device,Si_3N_4 and SiO_2-Si_3N_4-SiO_2-Si_3N_4( ONON) composite spacer were fabricated as the spacer of 45 nm NOR flash,gate disturb was measured under a programmed state and post cycling stress respectively.The influence of different spacer material on 45 nm NOR flash gate disturb was discussed.Although the application of Si_3N_4,spacer can improve the self-alignment contact( SAC) etch process,it could also bring larger threshold voltage shift during gate disturb due to its higher electric field across ONO.Meanwhile,the trapped charge during cycling could also bring negative effect on reliability of flash device.The NOR flash with ONON sidewall spacer has no reliability failure.Thus NOR flash with ONON sidewall spacer has better gate disturb performance than that with pure silicon nitride as a sidewall spacer.
出处 《半导体技术》 CSCD 北大核心 2017年第12期929-932,955,共5页 Semiconductor Technology
关键词 栅极干扰 侧壁隔离层 自对准接触 或非闪存器件 复合介质层 gate disturb sidewall spacer self-alignment contact (SAC) NOR flash compound dielectric layer
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