基于FPGA的低抖动时钟锁相环设计方法

Implementation of Calling PLL with Low Dithering Based on FPGA

锁相环作为FPGA内部重要的资源,已经广泛应用于各种系统中。首先介绍FPGA内部的时钟资源数字时钟管理器(DCM)和锁相环(PLL),随后采用FPGA逻辑调用PFGA内部PLL核,对锁相环的设计方法进行了探讨,最终通过示波器进行验证。同时,系统逻辑设计滤波,可以对输出时钟进行滤波,降低系统时钟抖动。系统具有一定的移植性,为系统调用PLL核提供一种方法。

Phase-locked loop（PLL） is widely used in many system,it is an important resource in FPGA. This paper mainly introduce the clock resource in PFGA ： Digital Clock Management （DCM） and Phase - locked loop（PLL）. Simultaneity, the transfer of inner PLL core in FPGA is introduced. The logic filter is combined in PLL system, thus the output clock signal has low dithering. This method can be used in many system, and it can provide a way to transfer the PLL core.