结深对65nm体硅CMOS晶体管单粒子瞬态脉冲的影响

Impact of junction depth on SET pulse width in 65nm bulk CMOS transistor

使用TCAD模拟工具,分析了纳米工艺下N+-N结、P+-P结和PN结深度的变化对PMOS以及NMOS单粒子瞬态(SET)脉冲宽度的影响,并考虑了电压温度变化下结深对晶体管单粒子瞬态的影响程度。结果表明,N+-N结的变化对PMOS晶体管单粒子瞬态脉冲宽度的影响最为显著。同时,还分析出N+-N、P+-P结在不同电压下的差异性较为明显,PN结在不同温度下的差异性较为显著。

We investigate the impact of N＋-N,P＋-P and PN junction depth on the single--event tran- sient （SET） pulse width in nano technology through TCAD simulations. The variations of voltage or temperature are also considered. Simulation results indicate that N＋-N junction plays the most important role in influencing the SET pulse width. Meanwhile, we also investigate the impact of voltage and temperature on junction depth. Simulation results indicate that the voltage can significantly affect N＋-N and P＋-P junction while the temperature can significantly affect PN junction.