一款深亚微米射频SoC芯片的后端设计与实现

The Back-end Design and Implementation of a Deep Submicrometer RF SoC

随着集成电路的发展,片上系统芯片(SoC)技术广泛应用于多种领域中,越来越多的射频、模拟、存储器模块集成到一块芯片中。SoC芯片后端设计面临尺寸特征小,芯片规模大,物理设计复杂程度高等问题。良好的芯片版图设计是集成电路实现和成功的基础之一。介绍了基于台积电0.18μm ULL低功耗工艺设计的射频SoC电路结构,在此基础上,详细说明了后端版图设计流程与布局规划,重点介绍了时钟模块设计,多时钟电路及复杂时序关系设计的后端布局处理,供电设计以及布线优化方法和技巧,对各类相关芯片的后端设计具有良好的借鉴意义。

With the development of integrated circuit, the system on chip （ SoC） technology is widely used in many applications, as more and more RF modules, analog modules and memory modules are embedded into one chip. The SoC back-end design confronts more challenges such as smaller feature size, larger chip area and more complex physical design. A remarkable layout design is one of the elements of the integrated circuit implemention and success. RF SoC circuit structure based on TSMC 0.18滋 mULL low power consumption process design is introduced,and on this basis, back-end layout design process and layout planning are explained in detail,mainly focusing on the clock generation module design, back-end processing method of multi-clock circuit and complex timing relationship design,power supply plan and layout optimization methods and techniques,that supplies a good reference to many relevant kinds of beck- end chip design.