一种超低相位噪声频率合成源方案设计

A Ultralow-phase-noise Scheme for Frequency Synthesizer

频率合成源是射频发生和频谱分析中最重要的组成之一,评价合成源性能指标的是输出信号的相位噪声、杂散、频率分辨率和频率切换时间.本文通过分析传统锁相环原理,提出一种通用的超低相位噪声合成源设计方案(带宽100 MHz以内).在锁相环基础上,通过引入直接数字合成(Direct digital synthesizer,DDS)混频鉴相技术,使得到的射频信号理论值达到0.1 m Hz的频率分辨率,同时将带内相位噪声指标优化17 d B以上.新方案同时兼顾了杂散和频率切换时间指标,保障合成源的输出信号稳定可靠,使其在自动测试领域拥有广阔的应用前景.

Frequency synthesizer is one of the most important component of RF generator and spectrum analysis. The performance of its output signal is evaluated in terms of phase noise, scattering, frequency resolution and frequency hopping time. By analyzing the traditional theory of phase-locked loop, a ultralow-phase-noise scheme for the frequency synthesizer is put forward （bandwidth within 100 MHz）. In order to make the frequency resolution of the output signal reach to 0.1 mHz in theory and optimize the in-band phase noise cver 17dB, direct digital synthesizer （DDS） and mixer phase detection technology based on phase-locked loop are introduced. Consideration is also given to both scattering and frequency hopping time to ensure the output signal is stable and reliable. The synthesizer has a good application in the field of automatic test.