AADL端对端数据流一致性验证方法

A Consistency Validation Approach of AADL End-to-end Flow Latency

复杂嵌入式实时系统的端对端数据流的时延分析是一种有效的实时系统实时性评估方法。体系结构分析与设计语言(Architecture Analysis and Design Language,AADL)是描述实时系统(嵌入式系统)的标准语言,端对端的数据流描述系统组件间的消息传递。提出一种基于Prolog的端对端数据流分析方法,解决嵌入式实时系统的AADL模型时延验证问题。针对AADL模型缺乏时延验证的现状,分析讨论了AADL模型的端对端数据流并提出了端对端数据流的路径一致性的定义;针对单一型端对端数据流和混合型端对端数据流给出了两种端对端数据流到基本状态图的映射方法;设计了端对端数据流路径一致性的Prolog验证规则。最后对带时间约束的汽艇速度控制子系统进行实例验证,结果表明该方法能够有效地解决实时系统的时延验证问题。

Time-delay analysis of end-to-end data streams of complex embedded real-time systems is an effective method of real-time system evaluation. The Architecture Analysis and Design Language （AADL） is a standard language that describes real-time systems （embedded systems） ,and end-to-end data streams describe message passing between system components. An end-to-end data flow a- nalysis method based on Prolog is proposed to solve the problem of AADL model latency verification for embedded real-time system. In view of the lack of time delay verification of AADL model, the end-to-end data flow of AADL model is analyzed and discussed, and the definition of path consistency of end-to-end data flow is proposed. For single end-to-eod and hybrid end-to-end data flow,two map- ping methods of end-to-end data flow to basic state diagram are given. A Prolog authentication rule is designed for end-to-end data flow path consistency. Finally, the time control of the speed control subsystem with time constraints is verified. The results show that the method can effectively solve the problem of real-time system delay verification.