基于FPGA的增量式编码器细分方法的研究

Research of incremental encoder subdivision method based on FPGA

为了精简增量式编码器信号处理系统的外围电路和实现在不增加编码器物理刻线的前提下提高编码器的分辨力和细分精度,提出一种基于FPGA的电子学细分方案,该方案可以获得较高分辨力和精度的编码器位置信息,且易于针对现场情况进行逻辑修改。该方案利用FPGA搭建细分方法所需要的各个模块,使用Modelsim软件进行仿真,并利用DA模块和示波器对该方案的数据进行验证分析。实验结果表明在编码器机械细分的基础上,该方案可以对信号进行120次细分,将增量式编码器分辨力提高至3″,并且可以将细分之后的机械角度精确至以度为单位的小数点后5位即10-5。

In order to streamline the periphery of the signal processing system of incremental encoder circuit and implementation without any increase in the encoder physical scribed line on the premise of improving the resolution of encoder and the subdivision accuracy, putting forward a kind of electronics subdivision seheme based on FPGA, this scheme ob- taining high resolution and precision of the encoder position information, easy to make logical changes according to field condition. This scheme using FPGA to build subdivision methods required for each module, Modelsim software for simu- lation, DA module and oscilloscope to verify the data of the program. On the basis of the experimental results show that mechancial subdivision in the encoder, the scheme can be 120 times the signal subdivision, the incremental encoder reso- lution up to 3＂, and can be , that is 10^-5 , subdivided after mechanical Angle preeisely to five decimal plaees for the unit.