基于多项式插值的分数延时滤波器的FPGA实现

An implementation of polynomial interpolation fractional delay filter based on FPGA

针对基于多项式插值的延时估计精度进行了分析研究。针对不同插值方法的延时估计精度进行了分析比较;指出了不恰当的分段二次插值延时估计存在局部极值问题,该局部极值会产生较大的延时估计误差;对分段二次插值多项式设计参数进行分析仿真得出恰当参数,在此基础上基于FPGA实现了一种可任意调节的分数倍延时滤波器,能够高速实时处理信号,既能保证延时估计精度,又可有效降低乘法运算量。

The precision of time delay estimation based on polynomial interpolation is analyzed in this paper. The different interpolation methods of time delay estimation accuracy are analyzed and compared.Simulations demonstrate that the inappropriate piecewise quadratic interpolation delay estimation is in the presence of local maxima problem. Such local maxima will produce larger time delay estimation error.The parameter of the piecewise quadratic interpolation polynomial are analyzed and the appropriate parameters are obtained. Eventually an arbitrarily adjustable FDF based on FPGA is presented. It can deal with the real-time data efficiently and guarantee the accuracy of time delay estimation,effectively reduce the implementation scheme of the number of multiplications.