用于波形数字化的JESD204B高速接口设计

Design of JESD204B High Speed Interface for Waveform Digitization

随着高速波形数字化技术在核与粒子物理实验中的广泛应用,其对于ADC速度和精度需求日益增大,从而使电子学系统的PCB布局布线更加复杂、成本更高。为了简化设计,降低成本,提出了用于波形数字化的JESD204B的高速接口设计方法,介绍了JESD204B接口的协议及需求,并提出了基于Altera FPGA和专用JESD204B时钟芯片LMK0482x的具体解决方案。测试结果表明,时钟性能优异且JESD204B链路功能正常,系统性能优异,该方法可以实现JESD204B高速接口设计,并应用于波形数字化技术。

At present, due to the wide application of nuclear and particle physics experiments in the waveform digitization technology and the increasing demand of high speed and high accuracy for ADC, the PCB layout is more and more complex and the cost is higher. In order to simplify the design and reduce the cost, this paper put forward the scheme of JESD204 B high speed interface for the waveform digitization technology in nuclear and particle physics experiments. Firstly the interface protocol and the demand of JESD204 B is introduced. Then the solution based on Altera FPGA and special JESD204 B clock chip LMK0482 x is proposed. The preliminary test results show that the clock performance is excellent and JESD204 B link is functioning normally. Moreover, the system has an excellent performance. The scheme can realize the design of JESD204 B high speed interface and therefore be applied to the waveform digitization technology.