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浮点及整数混合运算器的设计与实现 被引量:2

Design and Implementation for a Integer-Float ALU
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摘要 针对现行普遍的浮点运算器耗费面积较大,功能实现结构松散的问题,设计实现一款浮点及整数混合运算器(Mixture-Arithmetic Logic Unit,M-ALU).该运算器基于基4算法华莱士树型结构,并尝试一种新的阶码对齐方法,合并整数运算与浮点运算处理逻辑.在三级流水线结构下可准确完成单精度浮点数,扩展精度浮点数以及整数基本运算.采用基于synopsys提供的Design Compler综合工具在SMIC 65nm工艺库下完成综合,达到500MHz主频. For solve the issue that commont floating pointe ALU comsumes large area and srtucture loosely, afloating point and integer mixed operator M-ALU are designed and implemented. The algorithm based on the base-4algorithm Wallace tree structure, and try a new order code alignment method, merging integer arithmetic andfloating point arithmetic processing logic. In the three-stage pipeline structure can be accurately completed singlcprecision floating-point, extended precision floating-point and integer basic operations. Based on the synopsysprovided by the Design Compiler synthesis tool in the SMIC 65nm process library to complete the synthesis, to 500MHz frequency.
出处 《微电子学与计算机》 CSCD 北大核心 2018年第2期52-55,60,共5页 Microelectronics & Computer
关键词 IEEE754 SYSTEMVERILOG 乘加运算 整数 浮点 IEEE754 systemverilog multiply-add operations interger floating point
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