并联DC/DC系统中高速无线通信接收装置的设计

Design of High-speed Wireless Communication Receiver in Parallel DC/DC System

为了解决并联DC/DC控制系统中信息高频、单次传输量小的问题,就目前基带处理平台功能单一、灵活性差、运算效率低等问题,提出了一种改进型基带处理方案。该方案以FPGA+DSP为处理架构,依托高性能器件和高速接口搭建了基带处理平台。分别从基带处理和射频前端两个方面对无线通信系统接收装置进行硬件设计,重点研究基带处理DSP与FPGA的接口设计和零中频架构射频前端,通过FPGA对本地振荡器、A/D进行动态配置,采用基于BPSK的软件无线电平台,通过编写程序进行测试,结果验证了该方案满足科研要求,且具有一定的通用性和灵活性。

To solve the problems of high-frequency information and small amount of one single transmission in a parallel DC/DC control system,and considering the problems（e.g.,simple function,poor flexibility,and low computation efficiency） in the baseband processing platform at present,an improved baseband processing scheme was proposed. This scheme adopts FPGA＋DSP as the processing architecture,and a baseband processing platform was built based on high- performance devices and high-speed interfaces. The hardware of the wireless communication receiver was designed from two aspects, i.e.,baseband processing and radio frequency （RF） front-end,focusing on the study of interface design of ba-seband processing DSP and FPGA,as well as the zero-IF architecture RF front-end. Moreover,a dynamic configuration of local oscillators and A/D was realized through FPGA. A software radio platform was used based on BPSK,and programs were written to test the proposed scheme, which verified that the proposed scheme met the requirements of research, and it also had a certain generality and flexibility.