IIR数字滤波器设计与FPGA实现

Design and FPGA Implementation of IIR Digital Filter

提出了一种由FPGA实现六阶巴特沃斯带通IIR数字滤波器的解决方案。电路由三个二阶滤波器级联构成,采样频率为28.8k Hz时通带为1k Hz至3k Hz,适用于对幅频特性要求较高而对相频特性不敏感的领域。根据设计要求利用Matlab得到传递函数,根据Simulink模型仿真确定字长,使用CSD编码将滤波器系数优化为最少非零元素系统,从而减少了加法器级数。电路使用Verilog语言描述并通过FPGA实现,再用移位运算与加法运算代替浮点乘法来减少对FPGA资源的需求。实验测试结果符合理论设计,达到了预期的滤波效果。

This paper presents a solution to realize the sixth-order Butterworth band-pass IIR digital filter by FPGA. The circuit is composed of three second-order filters in cascade, and the passband is 1 k Hz to 3 k Hz when the sampling frequency is 28.8 k Hz, which is suitable for the field with high requirement to amplitude-frequency characteristics and insensitive to phase-frequency characteristics. Accord to design requirement, the transfer function is obtained by using MATLAB, the word length is determined according to Simulink model simulation, and the filter coefficient is optimized into a sytem with a minimum of non-zero elements by CSD coding, so as to reduce the adder series. The circuit is described in Verilog language and implemented by FPGA, and then shift operation and addition operation are used instead of floating-point multiplication to reduce the demand for FPGA resources. The experimental results accord with the theoretical design and achieve the desired filtering effect.