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纹理贴图的硬件实现与验证 被引量:1

Hardware implementation and verification of texture mapping
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摘要 三角形的纹理贴图是提升图形真实感的必要途径。介绍了一种新的纹理映射到三角形的硬件算法和FPGA实现的算法。该硬件算法每个时钟周期能够产生一个像素,并且经过透视正确纹理贴图结果渲染正确。立足于当前高性能图像处理器的需求,首先采用SystemC语言对于三角形纹理贴图进行行为模型,然后采用Verilog语言实现其硬件电路功能,同时使用FPGA开发板搭建验证平台完成三角形纹理贴图的功能验证。通过各方面验证,表明所设计的三角形的纹理贴图满足系统设计要求。 The texture map of triangles is the necessary way to enhance the realistic sense of graphics.This paper introduces a new hardware algorithm for mapping textures onto triangles and the FPGA implementation of the algorithm. The proposed hardware algorithm is able to produce a pixel each clock cycle and to render perspectively correct texture mapping. The paper is based on the current image processor requirements. Firstly,the behavioral model of triangle texture maps is established by using System C language, then the hardware circuit is realized by Verilog language, and the functional verification of triangle texture maps is accomplished by using a FPGAdevelopment board to build the verification platform. Through the verification of various aspects,it shows that the proposed hardware algorithm for triangle texture map of the triangle meets the system design requirements.
出处 《信息技术》 2018年第2期116-120,共5页 Information Technology
关键词 纹理贴图 投影变换 视窗变换 光栅化 硬件实现 texture map projection transform window transform rasterization hardware realization
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  • 1Garachorloo N, Gupta S. Sproull R F, et al. A Characterization of Ten Rasterization Techniques[C]//Proc. of the 16th Annual Conference on Computer Graphics and Interactive Techniques. New York. USA: ACM Press. 1989: 355-368.
  • 2Kaufman A. Rendering. Visualization, and Rasterization Hardware [M]. New York. USA: Springer-Verlag, 1993.
  • 3Ellsworth D A. Polygon Rendering for Interactive Visualization on Multicomputers[M]. NC. USA: Chapel Hill, 1996.
  • 4Kugler A. The Setup for Triangle Rasterization[C ]//Proc. of the 11th Eurographics Workshop on Computer Graphics Hardware. Poitiers, France: Eurographics Association. 1996: 49-58.
  • 5Crisu D, Cotofana S D, Vassiliadis S. A Hardware/Software Co-simulation Environment for Graphics Accelerator Development in ARM-based SoCs[C]//Proc. of the 13th Annual Workshop on Circuits. Systems, and Signal Processing. Veldhoven, The Netherlands: [s. n.], 2002.
  • 6Crisu D. Cotofana S D. Vassiliadis S, et al. Design Tradeoffs for an Embedded OpenGL Compliant Hardware Rasterizer[C]//Proc. of the 14th Annual Workshop on Circuits. Systems. and Signal Processing. Veldhoven. The Netherlands: [s. n.], 2003.
  • 7Evans A, Silburt A. Functional Verification of Large ASICs[EB/OL]. http://www.cs.ucr.edu/~dalton/refdesign/docs/nortel_verif_dac98.pdf, 1998-06-27.
  • 8Ferrandi F, Ferrara, Sciuto D. Testability Alternatives Exploration Through Functional Testing[EB/OL]. http://www.computer.org/proceedings/vts/0613/0613toc.html, 2000-05-05.
  • 9Fin A, Fummi F, Pravadelli G. AMLETO:A Multi-language Environment for Functional Test Generation[EB/OL]. http://profs.sci.univr.it/~pravadel/publications.html, 2001-11-25.
  • 10Corno F, Prinetto P, Sonza M. Testability Analysis and ATPG on Behavioral RT-level VHDL[EB/OL]. http://www.cad.polito.it/FullDB/exact/itc97.html, 1997-11-17.

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